Semiconductors are widely used in integrated circuits for electronic devices such as computers and televisions. These integrated circuits may contain millions of transistors fabricated on a single crystal silicon chip to perform complex functions and store data. Integrated circuits are commonly constructed by sequentially forming transistor active regions, insulating films, and patterned conducting films in a predetermined arrangement on a semiconductor substrate. Active regions and conducting films must be accurately aligned if the circuit is to function properly; therefore, self-aligning features (features whose placement is at least partially determined by the location of previously fabricated features) are highly desirable.
To facilitate extremely dense circuit layouts, it is desirable at times to fabricate the lowest conductor level (which typically includes transistor gates) with conductors at minimum spacing. Unfortunately, such spacing may make a self-aligned contact (SACT) necessary for, e.g., electrically connecting to source/drain active regions located in the narrow gaps between the conductors. One method for forming a SACT directly between closely spaced features is described by Bollinger, et al., in U.S. Pat. No. 5,200,358, issued on Apr. 6, 1993. In this method, first and second dielectric layers are deposited over gate level conducting features. A selective etch process is used to facilitate the opening of contact holes between the conducting features. The selective etch process is designed to remove material from the second dielectric layer faster than it removes material from the first dielectric layer. Silicon nitride and silicon dioxide (of different varieties) are used for the dielectric layers; relative etch selectivity for the best of such dielectric combinations is on the order of 10:1.
A method such as that described in the '358 patent is generally useful when the aspect ratio (ratio of gap height to gap width) of the gap between the conducting features is low; as the aspect ratio increases (which it generally does when device geometries shrink), the first dielectric layer must be made increasingly thick to insure that the insulation protecting the underlying conducting features will not be perforated during contact window etching. At some geometry, this method becomes ineffective for reliably forming such self-aligned contacts; the limited selectivity between dielectric layers and limited etch anisotropy (ability to etch in one direction only, e.g. vertically) make such a process difficult for high aspect ratio gaps.